3D IC: How Wafers, IDMs, and Packaging Factories Create New Relationships Are Key

The new architecture of 3D ICs has changed dramatically. It is not just the focus on front-end or back-end process execution. The key is how foundry foundry, integrated component manufacturers (IDM) and packaging plants create new relationships. The Wide I/O Memory Bus, which is the logic and memory die interface standard, was settled at the end of September, and hundreds of semiconductors have been added. This will help speed up the development process of manufacturers and promote early deployment of 3D ICs. Mass production.

Focusing on the importance of heterogeneous wafer bonding standards for the promotion of 3D ICs, the JEDEC JC 11.2 Standards Committee has been formed at a number of semiconductor plants, and the Wide I/O Memory Bus, an interface standard that has been pushing the logic to interface with memory chips, has been in late September. establish. In this way, through the standard follow-up and assistance, manufacturers can accelerate the development process, prompting 3D IC to start mass production as soon as possible.

Taiwan Semiconductor Manufacturing Co., Ltd. has targeted the business opportunities for 3D ICs and is actively attacking them. Through the integration of fabs, the company will extend its reach into the packaging field and is actively developing key technologies for 3D IC architecture, such as through-hole (TSV), and integrating existing crystals. Round Package (WLP) and Stacked Package (PoP) to create a complete 3D IC process solution.

The production process of 3D ICs must be perforated in the front-end wafer foundry process or implemented in the back-end packaging factory. From the fab’s standpoint, the introduction of the helium perforation process during the foundry phase is more competitive for the wafer industry because the fab has a better grasp of the overall wafer design and new investment. ] Less preparation costs to meet customers' control over production costs and accelerating time-to-market considerations. In addition, after wafers move into more advanced manufacturing processes, the technical thresholds for high-perforation punching are high, and packaging companies will have to invest more equipment, which will increase costs and do not meet customer's cost considerations.

Taiwan Semiconductor Manufacturing Co., Ltd. actively expands its business scope and seems to have caused the outside world to erode the concerns of package manufacturers. In this regard, Sun Moonlight believes that this is not only a reaffirmation of the importance of 3D IC packaging testing in the latter part of the industry, but also means that a new round of competition is about to begin and it is expected to affect 3D ICs. Industry and packaging industry have already compete for competition.é³’Y and the alliance sector, and promote the wafer foundry, packaging, testing industry to strengthen its own value of differentiation.

Sun Moonlight pointed out that 3D ICs will be the future chip development trend, and the supply chain will be reshuffled. This will lead to cross-industry integration, such as integration of semiconductors and micro-electro-mechanical (MEMS) and substrate and packaging and measurement industry cooperation embedded components technology (Embedded) . In addition, the new architecture of 3D ICs has changed dramatically, not only focusing on front-end or back-end process execution, but also on how foundry foundry, IDM (integrated component manufacturers) and packaging plants have created new vertical relationships. .